LDMOSFETs (laterally diffused MOSFETs) are known. Such devices are used as high-voltage switches and components in devices fabricated in various MOS process (fabrication) technologies including logic CMOS and the like but having relatively high-voltage requirements (e.g., 10 volts in a 3.3 volt process). Such high-voltages are used in charge pumps, programming nonvolatile memory circuits, on-chip LCD (liquid crystal display) display drivers, on-chip field-emission display drivers, and the like. A typical LDMOSFET 10 (also referred to as an LDMOS) is shown in elevational cross-section in FIG. 1. LDMOS 10 is fabricated in a p− substrate 12. A first n+ doped region 13 is disposed in first p− well 14 of substrate 12. A source terminal 16 is coupled to first n+ doped region 13. A p+ doped region 18 is disposed in second p− well 15. A body terminal 20 is coupled to p+ doped region 18. An n− well 22 is disposed in p− substrate 12 between first p− well 14 and second p− well 15. A first isolation structure 23 such as first trench 24 is disposed in n− well 22. An isolation structure 23 such as first trench 24 is filled with an insulating dielectric material such as silicon dioxide which may be deposited or grown in any convenient manner such as using the well-known Shallow Trench Isolation (STI) process (as shown) or the well-known Local Oxidation of Silicon (LOCOS) process (not shown). A second n+ region 28 is disposed in n− well 22. A drain terminal 30 is coupled to said second n+ region 28. Second isolation structure 25 such as trench 26 is disposed at least partially in n− well 22 and acts to isolate second n+ region 28 from p+ region 18. A layer of dielectric 33 is disposed over a portion of first p− well 14, the p− well/n− well junction region 34, a portion of n− well 22 and a portion of first trench 24 as illustrated. A gate region 32 is in contact with the dielectric layer 33 as well as the dielectric material in first trench 24. Gate region 32 may comprise n+ doped polysilicon material, p+ doped polysilicon material, metal, or any other suitable material used for forming a conductive gate. Insulating end caps 36 and 38 are also provided. The region denoted Lc is the channel of the device extending from the source region 14 to the first isolation structure 23, as shown, and Lc denotes its length. The region denoted Lw is a region of lateral diffusion under the gate and Lw denotes its length. The region denoted Lo is a region extending from one end of the channel to the end of the gate (where the gate extends over the first isolation structure 23), as shown, and Lo denotes its length. The region denoted Ldp is coextensive with the first isolation structure 23 and Ldp denotes its length. It provides gate isolation.
In this device the n− well is used as the drain of the device. A high breakdown voltage is provided due to lateral diffusion in the region denoted Lw under the gate. This results in deep junctions with lower doping than a typical n+ drain implant. The breakdown voltage is determined by the doping concentration of the n-well (approximately 1017/cm3) and p-well (approximately 1017/cm3) of the n-well/p-well junction. The prior art embodiment shown uses shallow trench isolation (STI). Similar embodiments implementing a LOCOS isolation scheme are also well known in the art.
As device geometries and minimum feature sizes (MFS) shrink, e.g., from 0.18 micron MFS to 0.13 micron MFS to 0.09 micron MFS and beyond, new ways to provide relatively high breakdown voltages, particularly in logic CMOS processes, become more and more important. Logic CMOS is important because it is commonly available at low cost with minimum process steps. Accordingly, it would be highly desirable to provide an improved high-voltage switching device.